1. Field of the Invention
The present invention generally relates to integrated circuits and a method of fabrication thereof, and more particularly, but not by way of limitation, to a wiring level of an integrated circuit in a back-end-of line processing.
2. Description of the Related Art
There has been a progressive trend toward miniaturizing electrical components though dimension scaling, thereby resulting in increased circuit density over time. The general manufacturing scheme of an integrated circuit (IC) can be divided into front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing.
Generally, in the FEOL processing, transistors and other active or nonlinear devices are formed on a semiconducting wafer surface, such as, for example, a Si wafer. In the BEOL processing, on the other hand, lower temperature processes are used to form multiple layers of interconnect wiring with damascene copper wiring being the most commonly used metallization process.
Conventional crystal and silicon devices require very high temperatures to form a transistor. For example, thermal growth of SiO2 requires approximately 1000° C. and dopant activation steps require from 600 to 1000° C. These steps at temperatures above 500° C. are incompatible with wiring fabrication, and therefore, the conventional technique is to form transistors in the FEOL, and then form the wiring interconnections in the BEOL using temperatures of 350-400° C. These limits and process order are critical to the success of conventional devices.
In conventional reprogrammable devices, known as a reprogrammable field programmable gate array (FPGA), the device takes advantage of a known method for reconfiguration of the chip. Specifically, a reprogrammable FPGA chip generally includes multiple logic elements (LE) or functional block units, wiring paths and programmable interconnections between the LEs. To properly function, connections are not only needed between the LEs and the wiring paths, but also between the wiring paths themselves.
These connections are formed through the programmable interconnections. For example, a programmable interconnection between two wires can be made by a pass transistor, e.g., a CMOS transistor, that is formed in the FEOL processing on the semiconducting wafer surface before the wiring paths are formed. The pass transistor's gate is controlled by a control voltage, which when high causes the pass transistor to become conductive and connect the two wiring paths. Likewise, when the control voltage is low, the transistor is off and the two wiring paths are not connected.
However, the pass transistor is not a perfect on-switch, which causes a large voltage drop across it, in turn leading to signal degradation, added power consumption, and/or lower speed at transmitting data through this switch.
In addition, in a conventional reprogrammable FPGA, a long wiring path exists to reach the pass transistor, said wiring path results in extra capacitance and significant resistance, which further slows down the device through RC delay.
As the size of the integrated circuit chip increases, so does the average interconnection wiring length. The increase in the average interconnect wiring length degrades the performance of the device via increased resistance and capacitance of the wires. As well, wire cross-sections scale down in more advanced technologies with smaller dimensions, increasing resistance per unit length even further.
Therefore, the present inventors have recognized that, there exists a need to decrease both the size of a conventional reconfigurable integrated circuit chip and its cost, while also increasing its performance.